`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/06/23 20:50:27
// Design Name: 
// Module Name: RF
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module RF(
    input clk,
    input rst,
    input [4:0] rs1,
    input [4:0] rs2,
    input [4:0] wR,
    input [31:0] wD,
    output reg [31:0] rd1,
    output reg [31:0] rd2,
    input rf_we
    );

reg [31:0] register[31:0];
integer i;

always @(*)
begin
    if (rst)
    begin
        rd1 <= 32'hzzzzzzzz;
        rd2 <= 32'hzzzzzzzz;
    end
    else
    begin
        rd1 <= register[rs1];
        rd2 <= register[rs2];
    end
end
always @(negedge clk or posedge rst)
begin
    if (rst)
    begin
        for (i=0; i<32; i=i+1)
            register[i] <= 0;
    end
    else if (rf_we)
    begin
        if (wR != 0)
            register[wR] <= wD;
        else
            register[wR] <= 0;
    end
    else
    begin
        for (i=0; i<32; i=i+1)
            register[i] <= register[i];    
    end
end

endmodule
